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cy7c1019d 1-mbit (128 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05464 rev. *g revised may 2, 2011 1-mbit (128 k 8) static ram features pin- and function-compatible with cy7c1019b high speed ? t aa = 10 ns low active power ? i cc = 80 ma @ 10 ns low cmos standby power ? i sb2 = 3 ma 2.0 v data retention automatic power-down when deselected cmos for optimum speed/power center power/ground pinout easy memory expansion with ce and oe options functionally equivalent to cy7c1019b available in pb-free 32-pin 400-mil wide molded soj and 32-pin tsop ii packages functional description [1] the cy7c1019d is a high-performance cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tri-state drivers. this device has an automatic power-down feature that significantly reduces power consumption when deselected. the eight input and output pins (io 0 through io 7 ) are placed in a high-impedance state when: deselected (ce high) outputs are disabled (oe high) when the write operation is active (ce low, and we low). write to the device by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight io pins (io 0 through io 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). read from the device by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appears on the io pins. a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe a 10 a 11 a 12 a 13 a 14 row decoder column decoder 128k x 8 array input buffer a 15 a 16 logic block diagram note 1. for guidelines on sram system design, please refer to the ?sys tem design guidelines? cypress application note, available on t he internet at www.cypress.com . [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 2 of 15 contents pin configuration ............................................................. 3 selection guide ................................................................ 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 switching characteristics ................................................ 6 data retention characteristics ....................................... 7 data retention waveform ................................................ 7 switching waveforms ...................................................... 7 read cycle no. 1 (address transition controlled) ..... 7 read cycle no. 2 (oe controlled) .............................. 7 write cycle no. 1 (ce controll ed) ............................... 8 write cycle no. 2 (we controlled, oe high during write) ...................................................... 8 write cycle no. 3 (we controlled, oe low) ............. 9 truth table ........................................................................ 9 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 3 of 15 pin configuration selection guide -10 (industrial) unit maximum access time 10 ns maximum operating current 80 ma maximum standby current 3 ma top view soj/tsopii 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 12 13 29 32 31 30 16 15 17 18 a 7 a 1 a 2 a 3 ce io 0 io 1 v cc a 13 a 16 a 15 oe io 7 io 6 a 12 a 11 a 10 a 9 io 2 a 0 a 4 a 5 a 6 io 4 v cc io 5 a 8 io 3 we v ss a 14 v ss [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 4 of 15 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [2] ..?0.5 v to +6.0 v dc voltage applied to outputs in high z state [2] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low)..... .................................... 20 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v cc speed industrial ?40 ? c to +85 ? c 5 v ? 0.5 v 10 ns electrical characteristics over the operating range parameter description test conditions -10 (industrial) unit min max v oh output high voltage i oh = ?4.0 ma 2.4 ? v v ol output low voltage i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage [2] ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v i < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc 100 mhz ? 80 ma 83 mhz ? 72 ma 66 mhz ? 58 ma 40 mhz ? 37 ma i sb1 automatic ce power-down current?ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?10ma i sb2 automatic ce power-down current?cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?3ma note 2. v il (min) = ?2.0 v and v ih (max) = v cc + 1 v for pulse durations of less than 5 ns. [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 5 of 15 capacitance [3] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 6 pf c out output capacitance 8 pf thermal resistance [3] parameter description test conditions 400-mil wide soj tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 56.29 62.22 ? c/w ? jc thermal resistance (junction to case) 38.14 21.43 ? c/w figure 1. ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: ?? 3 ns fall time: ?? 3 ns 30 pf* output z = 50 ? 50 ? 1.5v (b) (a) 5 v output 5 pf (c) r1 480 ? r2 255 ? high z characteristics: including jig and scope notes 3. tested initially and after any design or proce ss changes that may affect these parameters. 4. ac characteristics (except high z) are te sted using the load conditions shown in figure 1 (a). high z characteristics are tested for all speeds using the test load shown in figure 1 (c). [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 6 of 15 switching characteristics over the operating range [5] parameter description -10 (industrial) unit min max read cycle t power [6] v cc (typical) to the first access 100 ? ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z 0 ? ns t hzoe oe high to high z [7, 8] ?5ns t lzce ce low to low z [8] 3?ns t hzce ce high to high z [7, 8] ?5ns t pu [9] ce low to power-up 0 ? ns t pd [9] ce high to power-down ? 10 ns write cycle [10, 11] t wc write cycle time 10 ? ns t sce ce low to write end 7 ? ns t aw address set-up to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 7 ? ns t sd data set-up to write end 6 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [8] 3?ns t hzwe we low to high z [7, 8] ?5ns notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 7. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in (c) of figure 1 on page 5 . transition is measured when the outputs enter a high impedance state. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. this parameter is guaranteed by design and is not tested. 10. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the si gnal that terminates the write. 11. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 7 of 15 data retention characteristics over the operating range parameter description conditions min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?3ma t cdr [12] chip deselect to data retention time 0 ? ns t r [13] operation recovery time t rc ?ns data retention waveform switching waveforms read cycle no. 1 (address transition controlled) [14, 15] read cycle no. 2 (oe controlled) [15, 16] 4.5 v 4.5 v t cdr v dr > 2 v data retention mode t r ce v cc previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high icc isb impedance oe ce address data out v cc supply current notes 12. tested initially and after any design or proce ss changes that may affect these parameters. 13. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 ? s or stable at v cc(min) > 50 ? s. 14. device is continuously selected. oe , ce = v il . 15. we is high for read cycle. 16. address valid prior to or coincident with ce transition low.. [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 8 of 15 write cycle no. 1 (ce controlled) [17, 18] write cycle no. 2 (we controlled, oe high during write) [17, 18] switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce we data io address t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid note 19 ce address we data io oe notes 17. data io is high impedance if oe = v ih . 18. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 19. during this period the ios are in the output state and input signals should not be applied. [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 9 of 15 write cycle no. 3 (we controlled, oe low) [20, 21] truth table ce oe we io 0 ?io 7 mode power h x x high z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe note 22 ce address we data io notes 20. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 21. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 22. during this period the ios are in the output state and input signals should not be applied. [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 10 of 15 ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1019d-10vxi 51-85033 32-pin (400-m il) molded soj (pb-free) industrial CY7C1019D-10ZSXI 51-85095 32-pin tsop type ii (pb-free) ordering code definitions please contact your local cypress sales repr esentative for availability of these parts. temperature range: i = industrial package type: xxx = vx or zsx vx = 32-pin molded soj (pb-free) zsx = 32-pin tsop type ii (pb-free) speed: 10 ns d = c9, 90 nm technology 9 = data width 8-bits 01 = 1-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - 10 xxx 7 01 i d 9 [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 11 of 15 package diagrams figure 2. 32-pin (400-mil) molded soj (51-85033) 51-85033 *d [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 12 of 15 figure 3. 32-pin tsop type ii (51-85095) package diagrams (continued) 51-85095 *b [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 13 of 15 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable soj small outline j-lead sram static random access memory tsop thin small outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius a micro amperes s micro seconds mhz mega hertz ma milli amperes ms milli seconds mm milli meter ns nano seconds ? ohms pf pico farad vvolts wwatts % percent [+] feedback
cy7c1019d document #: 38-05464 rev. *g page 14 of 15 document history page document title: cy7c1019d, 1-mbit (128 k 8) static ram document number: 38-05464 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance information data sheet for c9 ipp *a 233715 see ecn rkf dc parameters are modified as per eros (spec # 01-2165) pb-free offering in the ordering information *b 262950 see ecn rkf added t power spec in switching characteristics table added data retention characteristics table and waveforms shaded ordering information *c 307598 see ecn rkf reduced speed bins to -10 and -12 ns *d 520647 see ecn vkn converted from preliminary to final removed commercial operating range removed 12 ns speed bin added i cc values for the frequencies 83mhz, 66mhz and 40mhz updated thermal resistance table updated ordering information table changed overshoot spec from v cc +2v to v cc +1v in footnote #2 *e 802877 see ecn vkn changed i cc spec from 60 ma to 80 ma for 100mhz, 55 ma to 72 ma for 83mhz, 45 ma to 58 ma for 66mhz, 30 ma to 37 ma for 40mhz *f 3110052 12/14/2010 aju added ordering code definitions . updated package diagrams . *g 3245896 05/02/2011 pras updated package diagrams . added acronyms and units of measure . updated in new template. [+] feedback
document #: 38-05464 rev. *g revised may 2, 2011 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1019d ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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